1. Technical Field
The present invention relates to a semiconductor device and an operation method thereof. Particularly, the present invention relates to a semiconductor device that controls mapping between a logical address requested from a host and a physical address of a memory device, and an operation method thereof.
2. Related Art
FIG. 1 is a block diagram illustrating a general memory system. The memory system may include a host 1 and a memory device.
The host 1 designates a logical address and requests the memory device 2 to perform a read/write operation. The memory device may include a control unit 3, a memory cell array 4, and a mapping table. The control unit 3 finds a physical address corresponding to the logical address with reference to the mapping table 30, and performs the read/write operation by using the physical address of the memory cell array 4.
When the memory device 2 is a NAND flash memory, page mapping, block mapping and the like are performed as a mapping scheme between a logical address and a physical address.
FIG. 2 is a diagram for explaining a conventional page mapping technology.
In the page mapping technology, the mapping table 30 stores a corresponding relation between a logical page address 10 managed by the host 1 and a physical page address 20 managed by the memory device 2.
To this end, the mapping table 30 should have storage areas 31 corresponding to at least the number p of the logical page addresses 10. Furthermore, the size of each storage area 31 should have enough data width to identify physical pages form one another.
For example, when the total number of physical pages is 2N, the data width of each storage area 31 is N, and thus, the size of the mapping table 30 is P×N.
As described above, the page mapping technology has a problem where as the number of physical pages (i.e., the size of the memory cell array 4) increases, the size of the mapping table 30 excessively increases.
FIG. 3 is a diagram for explaining a conventional block mapping technology.
In the block mapping technology, a page address is hierarchized into a block address and an offset number for management. FIG. 3 illustrates as an example in which one block includes two pages.
An offset number 12 of a logical page address and an offset number 22 of a physical page address correspond identically to each other. Accordingly, it is sufficient if the mapping table 30 stores a corresponding relation between a logical block address 11 and a physical block address 21.
In FIG. 3, since the number B of logical block addresses 11 is ½ of the number of logical page addresses, the number of storage areas 31 of the mapping table 30 used in the block mapping technology is reduced to ½ as compared to when the page mapping technology is employed.
Furthermore, since the number of physical block addresses 21 is also ½ of the number of physical page addresses, the data width of storage areas 31 of the mapping table 30 is also reduced. For example, when the number of physical pages is 2N, the number of physical blocks is 2N-1 and, thus the data width of storage areas 31 is reduced to (N−1).
When employing the block mapping technology, the size of the mapping table is reduced as compared to when the page mapping technology is employed.
However, since the corresponding relation between the offset number 12 of the logical block address 11 and the offset number 22 of the physical block address 21 is fixed, frequent write requests for the same logical address may also lead to frequent erasures for the corresponding page or memory cell.
FIG. 4 is a diagram for explaining a conventional partition recognition mapping technology.
In the partition recognition mapping technology, a page address is hierarchized into a partition number and an offset number.
A partition number 13 managed by the host 1 and a partition number 23 in the memory device 2 correspond to each other in a one-to-one manner. FIG. 4 illustrates as an example that two partitions are included.
The mapping table 30 is divided into two lower mapping tables 31 and 32 corresponding to the number of partitions.
The lower mapping table 31 stores a corresponding relation between an offset number 14 of a page belonging to a logical partition 0 and an offset number 24 of a page belonging to a physical partition 0 according to the page mapping technology.
The lower mapping table 32 stores a corresponding relation between an offset number 14 of a page belonging to a logical partition 1 and an offset number 24 of a page belonging to a physical partition 1 according to the page mapping technology.
In the partition recognition mapping technology, the number of storage areas of the mapping table is substantially the same as that of the page mapping technology, but the size of each storage area is reduced. As a consequence, the size of the mapping table in the partition recognition mapping technology is smaller than the size of the mapping table in the page mapping technology.
However, also in the partition recognition mapping technology, when a request is concentrated on a specific partition, the corresponding partition is quickly consumed as compared with other partitions, thereby reducing efficiency in using the entire storage space.